1. Field of the Invention
The present invention generally relates to a system for testing, and more particularly, to an electrical test system for testing a wafer.
2. Description of the Related Art
The high-speed parallel testing of a wafer-level semiconductor chip is presently limited to about 500 MHz. This is primarily caused by inherent limitations in probe cards utilized in parallel testing. Probe cards are known to achieve super-GHz high-speed testing, but these probe cards are used for serial (not parallel) testing. In other words, these probe cards are not adapted be applied to a wafer parallel test in which an electrical test is simultaneously performed on a plurality of semiconductor chips.
Electrical connection of a probe card with a performance board attached to a test head of a tester is generally made using a zero input force (ZIF) connector. The ZIF connector, however, can constitute a substantial source of signal loss.
FIG. 1 is a block diagram of a conventional electrical test system for a high-speed wafer parallel test, and FIG. 2 is a cross sectional view of a probe card used for the conventional high-speed wafer parallel test.
Referring to FIGS. 1 and 2, a performance board 20 is mounted on a test head 10 installed at one end of a tester. Also, a probe card 30 is connected to the performance board 20 using a ZIF connector 12 which, for example, tightens connected portions by means of a locking lever. An exemplary structure of the ZIF connector 12 is described in U.S. Pat. No. 7,077,675 B2, entitled “ZIF Connector In Which A Position Of A Contact Is Automatically Adjusted During A Connection Operation,” issued Jul. 18, 2006.
The conventional probe card 30 used for the electrical wafer parallel test includes a printed circuit board (PCB) 34 for a basic frame, a ZIF connector 34 connected to the performance board 20, an interposer 36, a multi-layer ceramic (MLC) substrate 38, and a plurality of needles 42.
The needles 42 are installed under the probe card 30 and connected to pads of semiconductor chips of a wafer 40. In this structure, an electrical parallel test can be performed on the wafer 40.
In order to confirm the high-speed parallel test limitations of the probe card 30, a simulation was conducted on the probe card shown in FIG. 2 using a vector network analyzer (VNA), which is a device for analyzing a frequency attenuation characteristic. In this analysis, the attenuation of a signal in a single path was measured as the frequency attenuation characteristic. The simulation result is that only a test frequency of 500 MHz was assured on the basis of −1 dB.
Loss of signals was measured in each of first through third paths as shown in the following Table 1. A first path for analysis was from the tip of the needle 42 to the MLC substrate 38, a second path for analysis was from the MLC substrate 38 to the interposer 36, and a third path for analysis was from the interposer 36 to the ZIF connector 32.
TABLE 1Loss atLoss atLossLoss at DC500 MHz1 GHzat 2 GHzAnalysis Path[dB][dB][dB][dB]Needle to MLC Substrate−0.19−0.46−0.70−1.23MLC Substrate to−0.00−0.01−0.03−0.10InterposerInterposer to ZIF−0.15−1.14−1.75−2.85ConnectorSum−0.34−1.61−2.48−4.18
As can be seen from Table 1, the greatest loss of signals occurred in the path from the interposer 36 to the ZIF connector 32 in the probe card 30.